1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular, to an input buffer circuit which cannot cause false operation by power noise.
2. Description of the Related Art
FIG. 1 shows a configuration of an ordinary semiconductor memory device. As shown, the memory device is made up of a row address buffer circuit 41, row decoder 42, memory cell array 43, column address buffer circuit 44, column decoder 45, sense amplifier 46, output buffer circuit 47, and chip enable buffer circuit 48.
The chip enable buffer circuit 48 receives an external chip enable signal CE. When the signal CE is a logic "0", the memory chip is in an active mode. When the signal CE is a logic "1", the memory chip is in a stand-by mode. The enable buffer 48 supplies an internal chip enable signal CEi to the row address buffer 41, row decoder 42, column address buffer 44, and column decoder 45. These circuits 41, 42, 44 and 45 are controlled by the internal chip enable signal CEi. In the stand-by mode, the power dissipation of those circuits is reduced. In other words, the power dissipation of the memory chip is controlled by the external chip enable signal CE. The output buffer circuit 47 rapidly charges or discharges an external large load capacitor by means of a transistor having a large current drive capability. A typical circuit arrangement of the output buffer 47 is shown in FIG. 2.
In FIG. 2, a signal denoted as OEl is an output enable signal outputted from a control pulse signal generator (not shown) provided in the memory device of FIG. 1. A signal denoted OEl is the inverted signal of the signal OEl. When the signal OEl and OEl are a logic "1" and a logic "0" respectively, the data Di derived from the memory cell array 43 of FIG. 1 is applied as potential Va to the gate of a p-channel MOS transistor 56 through a NOR gate 52 and an inverter 54. Also, the data Di is applied as potential Vb to the gate of an n-channel MOS transistor 57 through a NAND gate 53 and an inverter 55, the transistor 56 or 57 being selectively turned on thereby, in accordance with the data Di from the cell array 43.
When the transistor 56 is turned on, an output terminal 58 is charged toward a potential of a power source terminal Vcc. As a result, output data Dout of a logic "1" is outputted at the output terminal 58. When the transistor 57 is turned on, the output terminal 58 is discharged toward a ground potential. As a result, output data Dout of a logic "0" is outputted. To rapidly charge and discharge the output terminal 58 connected an external large load capacitor 60, the current drive capability of each of the transistors 56 and 57 is large.
The output buffer 47 is connected to an external power source 70 through line L1 and line L2 The circuits shown in FIG. 1 are all coupled with the line L1 and the line L2. Those lines L1 and L2 contain parasitic inductances 71 and 72, respectively. Because of the presence of those inductances, the power-source potential Vcc or the ground potential Vss in the memory chip is varied, when current Is or It flows through the transistor 56 or 57 respectively for charging or discharging of the output terminal 58.
Assuming that the value of each inductance L1 and L2 is L, and the rate of change of current "i" flowing through those inductances with respect to time "t" is di/dt, a potential variation .DELTA.V of each of the power-source potential Vcc and the ground potential Vss in the memory chip can be expressed by EQU .DELTA.V=L.multidot.(di/dt).
Such a potential variation is called a power noise.
A timing chart shown in FIG. 3 describes the relation of operation-states of the output buffer 47 to power noise. As seen from the figure, when the transistor 56 is turned on and the current Is flows, the power-source potential Vcc in the memory chip temporarily swings in the negative direction, and then swings in the positive direction. When the transistor 57 is turned on and the current It flows, the ground potential Vss in the memory chip temporarily swings in the positive direction, and then swings in the negative direction.
Such variations of power source voltage may cause false operation of each of the circuits of the memory device shown in FIG. 1. The probability of the occurrence of the false operator is particularly high in the input circuits receiving external signals, such as the row address buffer 41, column address buffer 44, and chip enable buffer 48.
Such false operation caused by power noise will be described with reference to the row address buffer 41 and the chip enable buffer 48. A typical circuit arrangement including the row address buffer 41 and the chip enable buffer 48 is illustrated in FIG. 4. The row address buffer 41 receives an external address signal which is generated by another integrated circuit. Accordingly, even if the power source potential in the memory chip varies, the potential of the address signal does not vary. It assumes that an address signal of a logic "0" is applied to the row address buffer 41. If the ground potential Vss varies in the negative direction, the row address buffer 41 which decides the logic level of the input signal with respect to the ground potential Vss may mistakenly recognize this logic "0" signal as a logic "1" signal, because a difference between the potential of the input signal and the ground potential Vss grows.
In a conventional technique, a C-R delay circuit TC is provided at the prestage of the row address buffer 41, in order to prevent the memory device from false operation. With the use of the circuit TC, the input terminal of the row address buffer 41 is coupled with the ground potential Vss through the capacitor C. Accordingly, when the ground potential Vss varies, the potential at the input terminal of the buffer 41 also varies. This fact indicates that even if the power voltage varies, the difference between the input terminal potential and the ground potential is not changed. Therefore, the row address buffer 41 will not mistakenly recognize the logic level of the address signal.
The chip enable buffer 48, like the row address buffer 41, sometimes mistakenly recognizes the logic level of an external chip enable signal CE when the power source potential varies. In the chip enable buffer 48, it is not preferable to provide the C-R delay circuit TC at the prestage of the buffer 48. The reason for this is that such a provision of the circuit TC would have an adverse effect on the access speed performance of the memory device.
Generally, a semiconductor memory device has two modes of read operation. In the first read mode, data is read out of the memory chip in such a manner that when the memory chip is in an active state, the address signal is changed. In the second read mode, data is read out of the memory chip in such a manner that when the address signal remains unchanged, the operation state of the memory chip is changed from a stand-by state to an active state. The data read speed of the second mode is than the data read speed of the first mode. The reason for this is as follows. The row address buffer 41 is controlled by the internal chip enable signal CEi from the chip enable buffer 48. When the state of the memory chip changes from the stand-by state to the active state, the row address buffer 41 responds to the internal chip enable signal CEi which changes after a given retardation from the change of the external chip enable signal CE. Accordingly, the row address buffer 41 starts to operate after the response time of the chip enable buffer 48. In other words, the data read speed when the chip enable signal CE changes is slower than that when the address signal is changed, by the response time of the chip enable buffer 48.
In the case where the C-R delay circuit TC is provided at the prestage of the row address buffer 41, the data read speed when the address signal changes is delayed by delay time of the C-R delay circuit TC. However, the read speed of the memory device does not suffer any damage, if the delayed data read speed when the address signal changes is not slower than that when the chip enable signal CE is changed. However, if the C-R delay circuit TC is provided at the prestage of the chip enable buffer 48, the data read speed when the chip enable signal CE changes, viz., the data read speed of the memory device is slowed by the delay time of the C-R delay circuit TC.
Accordingly, since the C-R delay circuit TC cannot be provided at the prestage of the chip enable buffer 48, the chip enable buffer 48 is susceptible to power noise. The logic level of the internal chip enable signal CEi may be inverted by the power noise, as previously mentioned, and all of the circuits that are controlled by the internal chip enable signal CEi will malfunction.